Staff Physical Design Engineer, Timing

Responsibilities: In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime. Own all aspects of the timing convergence, including Signoff to build timing correlation, PVTRc corner definition, timing margining, extraction, signoff timing analysis, glitch noise analysis, timing ECOs and interplay and tradeoff with power. Own, define and drive constraints in collaboration with RTL and IP Vendors. Have in-depth understanding of all timing collaterals for different type of Ips, namely, hard IP, Stdcell and Memory etc. Partner with post-si bringup and testing to ensure pre-si timing correlates well to post-si. Collaborate closely with RTL designers, DFT and other stakeholders to achieve best in class PPA. Continuously improve timing analysis methodologies and scripts to enhance efficiency and flow consistency. Stay at the forefront of advancements in STA and new process nodes

Qualifications: Master's degree in Electrical Engineering or Computer Engineering (or a related field) Minimum of 5 years of experience in Timing Analysis and convergence. Proven expertise in static timing analysis using industry standard timing tools like primetime (Synopsys) or tempus (Cadence). In-depth understanding of digital circuit design principles and concepts Strong proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence) Excellent analytical and problem-solving skills Ability to work effectively in a team environment and communicate complex technical concepts clearly Experience with scripting languages (e.g., TCL, Python) Experience with PnR tools like Fusion Compiler (Synopsys) and Innovus (Cadence) is a plus. Seniority level Seniority level Mid-Senior level Employment type Employment type Full-time Job function Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at Acara Solutions, An Aleron Company by 2x Get notified about new Physical Design Engineer jobs in Austin, TX. Austin, TX $106,500.00-$162,000.00 21 hours ago Austin, TX $136,000.00-$264,500.00 1 day ago Austin, TX $139,360.00-$209,040.00 1 week ago Austin, TX $114,000.00-$133,000.00 1 week ago Austin, TX $212,000.00-$291,000.00 1 week ago Physical Design Engineer, Annapurna Labs Austin, TX $104,000.00-$212,200.00 2 weeks ago ASIC Physical Design Engineer, Annapurna Labs 2025 Summer Intern-Physical Design Engineer Austin, TX $142,000.00-$203,000.00 1 week ago Sr. Physical Design Engineer, Annapurna Labs Austin, TX $143,300.00-$247,600.00 2 weeks ago Austin, TX $212,000.00-$291,000.00 1 week ago Lead Physical Design Engineer, Full Chip Implementation Austin, Texas Metropolitan Area 1 day ago Austin, TX $120,000.00-$165,000.00 3 weeks ago Physical Design Methodology Engineer for High Performance / Low Power Designs Austin, TX $171,200.00-$256,800.00 3 days ago Austin, TX $171,200.00-$256,800.00 1 day ago Austin, TX $142,000.00-$203,000.00 1 week ago Physical Design and Verification Engineer Austin, TX $142,000.00-$218,000.00 5 months ago Senior Physical Design Methodology Engineer Austin, TX $168,000.00-$310,500.00 2 weeks ago Senior ASIC Physical Design Engineer - High Performance Designs Austin, TX $136,000.00-$264,500.00 1 week ago Physical Design Methodology Engineer, Annapurna Labs Austin, TX $129,800.00-$212,800.00 2 weeks ago VLSI Design Engineer for Server / Data Center Products We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.