Senior ASIC Design Engineer – Clocks IP

Responsibilities: Architect clock domains to meet functional, physical, and testing requirements Collaborate with GPU/CPU design, physical design, timing, and verification teams to address clocking constraints Evaluate DFx, Physical Implementation, and Power Optimization trade-offs to improve PPA and implement new clocking topologies in RTL Develop clocking solutions with physical design and timing teams for high-speed operation Deliver clock RTL information to verification, timing, and DFT teams and support silicon bring-up Participate in end-to-end ASIC execution from micro-architecture and design fixes to sign-off and silicon bring-up

Key requirements: BS in Electrical Engineering or equivalent experience (MS preferred) 3+ years of relevant work experience Deep understanding of logic optimization techniques and PPA trade-offs Excellent interpersonal skills and ability to collaborate with multiple teams Experience in RTL design (Verilog), verification and logic synthesis Strong coding skills in Python or other industry-standard scripting languages Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus Implementing on-chip clocking networks is a bonus interpersonal skills cross-team collaboration ability to communicate complex concepts clearly RTL design (Verilog) verification logic synthesis