EXOS is seeking a Senior SRAM Layout Design Engineer to own the complete custom layout process for SRAM bitcells, periphery, test structures, and memory macros in advanced CMOS nodes. You will collaborate with circuit, CAD, and foundry teams to deliver high-quality memory IP and mentor junior engineers. The role emphasizes hands-on ownership of layout, floorplanning, DRC/LVS checks, and advancing layout methodologies on cutting-edge process technologies.
