Design Verification Engineer – Contract Palo Alto, California | Remote Considered | ContractIC Resources is working with a stealth-mode startup semiconductor company developing next-generation silicon design tools using advanced AI systems. This role will involve owning verification for SoC blocks and subsystems, from testbench architecture through to coverage closure and signoff, across real customer programmes. You will be required to visit the site 1 week per month
Key responsibilities:- Own verification plans, testbench architecture, and signoff
- Develop SystemVerilog/UVM environments, sequences, scoreboards, and checkers
- Verify PCIe, Ethernet, CPU integration, interconnects, and switches
- Run regressions, track coverage, and debug failures
- Set up verification flows for new programmes
- Use AI-assisted tools for test generation, debug, and coverage closure
- Work directly with customer design and verification teams
- Key experience required:6+ years of hands-on Design Verification experience
- Multiple production tapeouts
- Strong SystemVerilog and UVM experience
- Experience with Arm CPU clusters, interconnects, PCIe, Ethernet, or CPU/subsystem integration
- Strong debugging and verification skills
- Ability to work independently in fast-paced environments
- Desirable experience:
- Formal verification and SVA, Using JasperGoldAMBA, PCIe, or Ethernet VIPEmulation or hardware-accelerated simulation
- Consulting or contract engineering experienceAI-assisted verification tools
If you are interested and would like further information, please contact Chase Jacobs at IC Resources.
