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OLIX is seeking a Senior Analog Layout Designer to create RX/TX lane macros and support lane-level integration for the DX-1 accelerator family. You will drive advanced layout efforts across multiple FinFET nodes and ensure robust LVS/DRC/DFM verification. Ideal candidates have extensive experience with Cadence Virtuoso, Calibre, and Pegasus, plus strong cross-functional collaboration and scripting in Python or TCL. This is a fast-paced, highly technical environment in Austin.

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Level

Lead L6

Location

Austin, TX

Occupation

Electronics Engineers, Except Computer

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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