Lead the critical "make vs. buy" decision for the future of DDR PHY IP and define the multi-year AMS roadmap for SoCs. Own the overall Power, Performance, and Area (PPA) envelope for the entire memory subsystem, dictating trade-offs and ensuring DDR access meets the extreme, high-stakes requirements of on-device GenAI models. Direct the integrated AMS and PMIC teams, ensuring high-quality execution of the immediate optimization roadmap. Build the talent and organizational structure required for the long-term strategic vision, including building and scaling strategic teams or capabilities. Act as the technical and strategic liaison to executive leadership, driving organizational alignment and securing resource commitments across high-leverage internal stakeholders (CPU, TPU, system architecture, and product teams).
Minimum qualifications:
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.15 years of experience with custom silicon design (SoCs, ASICs, etc.).10 years of experience in people management and developing employees.
Experience in high-speed analog mixed-signal design, specifically in DDR PHY/LPDDR interfaces.
Experience with analog and digital mixed-signal design (AMS, DMS).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.10 years of experience with analog and digital mixed-signal design with a deep understanding of both disciplines.
Experience leading cross-functional IP development and SoC integration.
Experience with bleeding-edge process nodes in silicon foundries.
Experience across silicon engineering topics from architecture and implementation to productization and high-volume manufacturing.
Understanding of the systemic challenges related to power, performance, and thermal management in mobile and AI SoCs.
As the Director of Analog Mixed-Signal Silicon you will lead the strategy and execution of cutting-edge mixed-signal IP development for Google's consumer hardware products. The Google Silicon team develops custom silicon solutions that provide differentiated user experiences, and this role will define the multi-generational AMS strategy to establish a persistent competitive advantage for platforms like Tensor and Pixel.
You will execute an optimization roadmap for the next three generations of the Tensor SoCs—a mandate made vital by the extreme power and performance demands of GenAI and Gemini applications. Beyond immediate execution, a core strategic function is to define the future of the PHY IP, planning whether to transition to in-house design or secure a solution through a new 3rd Party Optimization (3PO) partnership.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $281000 - $391000 (USD) + 30% bonus target + equity + benefits
Learn more about benefits at Google.
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.15 years of experience with custom silicon design (SoCs, ASICs, etc.).10 years of experience in people management and developing employees.
Experience in high-speed analog mixed-signal design, specifically in DDR PHY/LPDDR interfaces.
Experience with analog and digital mixed-signal design (AMS, DMS).
