Physical Design Manager
quest globalSan Jose, CA
$180,000 - $240,000 per year
APPLYPhysical Design Manager
quest globalSan Jose, CALead L6
$180,000 - $240,000 per year
Electronics Engineers, Except ComputerArchitectural and Engineering ManagersComputer Hardware Engineers
Computer Systems Design ServicesSemiconductor and Related Device ManufacturingResearch and Development in the Physical, Engineering, and Life Sciences (except Nanotechnology and Biotechnology)
APPLY NOWWe are looking for a highly experienced Physical Design Managerto lead and execute complex ASIC physical design activities fromRTL to Tape-out. The ideal candidate will have extensive hands-on expertise in advanced-node physical implementation, timing closure, physical verification, and methodology development. Strong proficiency inCadence Innovusis mandatory and non-negotiable.
Location: San Jose, CA
Key Responsibilities:
- Lead and execute end-to-end Physical Design implementation for complex SoCs and ASICs.
- Perform RTL setup, synthesis, and optimization to achieve Power, Performance, and Area (PPA) targets.
- Drive timing closure through advanced STA methodologies and optimization techniques, including top-level timing analysis.
- Execute and analyze EM/IR verification to ensure robust silicon implementation.
- Own Place & Route activities, congestion management, and design optimization.
- Develop and implement Clock Tree Synthesis (CTS) strategies, including custom clock tree design, skew balancing, and insertion delay reduction.
- Mandatory SkillsStrong hands-on expertise with Cadence Innovus (Mandatory / Non-Negotiable)
- Full-chip Physical Design experience fromRTL to Tape-out
- Top-level STA and Timing Closure expertise
- Floorplanning, CTS, Place & Route, Physical VerificationEM/IR Analysis and Sign-off Flows
Preferred Qualifications:
Expertise in industry-standard EDA tools and implementation methodologies.
Experience with advanced technology nodes and complex SoC designs.
Excellent problem-solving, leadership, and communication skills.
Ability to mentor junior engineers and drive technical decisions.
Education & Experience:
Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.12+ years of relevant experience in ASIC/SoC Physical Design. Proven track record of delivering successful tape-outs.
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Level
Lead L6
Salary
$180,000 - $240,000 per year
Location
San Jose, CA
Occupation
Electronics Engineers, Except Computer
Industry
Computer Systems Design Services
Posted
2 days ago