Eliyan is building NuLink, a proprietary die‐to‐die chiplet interconnect fabric purpose‐built for AI infrastructure at hyperscale. As Eliyan expands into co‐packaged optics (CPO), the VP of Optical Product Development owns the product strategy for integrating third‐party optical components — VCSELs, photodetectors, lenses, and fiber interfaces — with Eliyan's silicon die at the package level. This role requires deep familiarity with semiconductor fabrication and assembly processes, as all optical integration decisions are constrained by and executed within a semiconductor packaging environment.
Key Responsibilities:
Define optical product strategy centered on die‐level co‐packaging of external optical components with Eliyan's silicon. Own the optical component selection and qualification process (VCSELs, PDs, lenses, fiber connectors), evaluating vendors against system performance and assembly compatibility requirements. Drive assembly‐aware optical product specifications — accounting for flip‐chip tolerances, solder reflow constraints, alignment accuracy, and packaging design rules. Engage silicon process and design teams on equal footing, translating optical requirements into process‐compatible constraints and vice versa. Navigate optical‐electrical co‐design tradeoffs within foundry process boundaries (e.g., TSMC, GlobalFoundries, or equivalent). Serve as the primary interface between optical and silicon teams (analog/digital), ensuring bidirectional feed‐in/feedback between optical integration requirements and silicon design. Partner with Marketing to define product positioning, customer‐facing optical specifications, and roadmap priorities. Report execution status and product milestones to the COA.
Qualifications:
12+ years in optical systems or photonic integration, with substantial hands‐on experience in semiconductor fabrication, assembly, or advanced packaging environments. Solid working knowledge of semiconductor fabrication processes — FEOL/BEOL concepts, lithography constraints, metal layer stackups, and how process design rules affect optical integration feasibility. Deep understanding of co‐packaging architectures — flip‐chip bonding, micro‐bump interconnects, interposer‐based integration, or equivalent. Experience qualifying and integrating third‐party optical components (VCSELs, PDs, optical subassemblies) into semiconductor packages. Familiarity with packaging design rules and their implications for optical alignment yield. Experience navigating optical‐electrical co‐design tradeoffs within foundry process boundaries. Strong cross‐functional communication skills across silicon, packaging, and marketing teams. Standards‐body experience (IEEE 802.3, OIF, CPO Consortium) a plus. We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.
