Tensordyne in Sunnyvale, CA seeks an experienced ASIC STA lead to guide and implement frontend physical design timingClosure for multimodal AI inference chips. This hands-on role focus on hierarchical STA, full-chip signoff, and optimization of Genus/Innovus workflows with Cadence/Synopsys tools.
You will collaborate with a global engineering team in a fast-paced startup, mentoring peers, writing SDCs for high-speed interfaces, and driving innovative EDA solutions to meet aggressive performance,
