ASIC Engineering Technical LeaderWe are seeking a motivated, proactive, and intellectually curious ASIC Engineering Technical Leader with a strong focus on Design-for-Test (DFT). In this role, you will lead the development and implementation of DFT solutions for next-generation ASICs supporting multi-100G through 1.6T coherent optical communications products.
Key Responsibilities:- Lead the implementation of SSN-based test-flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST.Utilize Siemens Tessent tools for RTL and gate-level netlist DFT implementation.
- Generate and deliver ATPG test patterns for: Stuck-at fault models
- Transition fault models
- Cell-aware fault models
- Path-delay fault models
- Drive scan-based diagnosis methodologies for silicon failure debugging.
- Provide post-silicon testing, validation, and troubleshooting support.
- Evaluate design readiness for scan insertion using RTL and physical-design Scan Design Rule Check (DRC) tools.
- Integrate and verify Design-for-Test (DFT) fabrics and IP within subsystems.
- Perform and debug non-timing and back-annotated timing (SDF) gate-level simulations.
- Develop test scripts, automate engineering processes, and analyze data using programming languages such as Python, Tcl, or C++.Support DFT execution throughout the ASIC development lifecycle, including design, verification, tapeout, and post-silicon validation.
Minimum Qualifications:- Bachelor's degree with 8+ years of related experience, ORMaster's degree with 6+ years of related experience, ORPhD with 3+ years of related experience.
- Prior experience working with ASICs.
- Hands-on experience with scan insertion and DFT setup, integration, and validation.
- Experience implementing DFT architectures, including: Scan insertion
- Compression/decompression logic
- Memory BISTLogic BIST
Preferred Qualifications:
10+ years of experience working with ASICs.10+ years of experience with scan insertion and DFT setup, integration, and validation.3+ years of experience with SSN.Experience driving ASIC DFT execution from concept through tapeout.
Experience working with ATE testers and test engineering teams.
Strong RTL knowledge with the ability to understand and debug DFT-related issues.
Ability to solve complex technical problems, including clock-domain crossing (CDC) issues.
Familiarity with advanced silicon processes and technology nodes designed for high-speed and low-power applications.
Strong experience implementing or integrating design blocks using Verilog/System
Verilog.
All qualified applicants will be considered without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.
