Senior FPGA/ASIC Co-Design Engineer

AMD in San Jose is seeking a hardware/FPGA design engineer to architect and implement high-performance ASIC/FPGA acceleration solutions, collaborating with architects and firmware teams. You will develop RTL in SystemVerilog/Verilog, verify complex logic, and lead pre-silicon verification and post-silicon bring-up across PCIe, CXL, Ethernet, and DDR5/6. This role requires strong problem-solving, system-level validation, and scripting with Python/Tcl; you will work with global teams in a