Job TitleResponsibilities: Develop and maintain UVM-based verification environmentsVerify CPU subsystems and instruction executionImplement constrained-random testingIntegrate Instruction Set Simulators (ISS) with DV environmentsDebug complex functional issues across hardware and testbenchRequirements:5+ years Design Verification experienceStrong skills in: SystemVerilogUVMTestbench architectureExperience verifying processor or CPU subsystemsPreferred: Familiarity with Instruction Set Simulators (Spike or similar) Experience with random instruction generators (Sting) Knowledge of processor software toolchains
