Principal ASIC Design Engineer - RTL & Silicon Bringup

SiMa.ai, Inc. in San Jose, CA is seeking a Principal ASIC Design Engineer to own complex RTL blocks from concept through silicon bring-up. The role emphasizes hands-on Verilog/System Verilog, block-level optimization, and collaboration with verification, physical design, and firmware teams in a fast-paced startup environment. You will drive ground-up design, timing closure, and DFT readiness while focusing on power, performance, and area targets.