Architect is seeking a technically seasoned RTL Design staff member to own AI-driven microarchitecture and RTL for high-performance networking subsystems. You will define block-level specs for Ethernet MAC engines, IPv4/IPv6-like datapath considerations, and tight integration into production silicon. The role requires 5+ years in RTL design with advanced-node tapeout in NICs or switches, SystemVerilog mastery, and strong collaboration with DV, SW, and ML teams to refine timing, area, and power
