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Annapurna Labs (U.S.) Inc. seeks a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for next-generation ML and data center ASICs. You will own the package layout from floor planning through tape out and manufacturing release, coordinating with silicon, SI/PI, thermal, and manufacturing teams to meet performance and reliability targets. Responsibilities include overseeing 2.5D/3D-IC packaging, flow planning, DFM, and cross‑level optimization across die,

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Level

Lead L6

Location

Austin, TX

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

10 days ago

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