Design Verification Engineer-W

Job Title: Design Verification Engineer

Location: San Jose , CA Remote

Experience level: 8-12 years 12+ years of experience in SOC/IP/block level functional verification using System Verilog/UVM.Must have executed at-least 1 to 2 SoC/IP Verification projects on C++ based verification environment Knowledge of Ethernet PCS layer, and or OTN G709 is required. Strong knowledge of C++UVM and System Verilog added advantage. Must have worked on development of test plan, testbench components, verification environment, interface agents, Scoreboards. Understanding of complete functional verification cycle will be added advantage Skills to debug RTL & testbench issues, test failures. Experience on verification closure by closing Coverage and bug reports Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc

Skills: System Verilog, UVM, C++