Seeking a full-time remote Senior ASIC Verification Engineer, the candidate will be responsible for verification closure of projects including design modules and SoCs, driving test planning and UVM-based testbench development while collaborating with cross-functional teams to ensure high design quality.
Key responsibilities:
Define overall SOC level verification strategy and technical planning
Develop and execute functional tests according to verification test plans
Collaborate with design, software, emulation, and silicon validation teams to ensure design qualityRequired qualifications:8+ years of experience in ASIC verification with UVM/System Verilog
Hands-on experience in verifying complex SoCs with multiple clock and reset domains
Experience in ground-up testbench development and debugging using Verdi or equivalent tools
Familiarity with revision control systems like Git or SVN
B.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
