Palo Alto Networks, Inc. is seeking an experienced ASIC design professional to own frontend design from spec to silicon bring-up for our next‑gen firewall platforms. You will work with verification and physical‑design teams to hit aggressive performance, power, and schedule goals. Responsibilities include writing micro-architecture specs, creating SystemVerilog RTL, and verifying blocks through simulation, emulation, and formal methods, with a focus on robust, scalable designs.
