RTL Design Manager for Front-End SoC Innovation

AMD is seeking an RTL Design Manager for the AECG IP & SOC group in San Jose, CA. You will lead a small team, own RTL block design, and guide verification while driving automation to improve efficiency. Strong front-end RTL background and clear communication with executives are essential. The role collaborates with architecture, IP design, and Physical Design teams to ensure first-pass silicon success and scalable design practices.