Power-Driven ASIC Engineer: EDA Flows & Signoff

Meta is seeking an ASIC Engineer specialized in power on the EDA Infrastructure team in Austin to build and optimize power analysis flows and signoff methodologies across RTL to GDSII. You will collaborate with RTL, physical design, and verification teams to reduce power hotspots and drive efficiency in custom ASIC designs. The role involves developing scripts, evaluating EDA tools, and defining power methodology guidelines to support next-generation silicon design and verification at Meta.