Silicon Design Package Designer
Location: Santa Clara, CA (Onsite)
This role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologies.
Key Responsibilities:
Tools Knowledge: Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).Technical Expertise: Multi-layer package design experience. Understanding of substrate manufacturing Design Rules and Assembly Rules. Familiarity with SIPI (Signal Integrity Power Integrity) Rules. Flip-chip package design concepts.
Tasks:
Perform point-to-point connections.
Run DRC (Design Rule Checks), identify root causes, and fix issues.
Execute design based on provided schematics, including component placement and constraint setup.
Regarding Equal Employment Opportunity:
*** is an Equal Employment Opportunity employer. We promote and support a diverse workforce at all levels of the company. All qualified applicants will receive consideration for employment without regard to race, religion, color, sex, age, national origin or disability. All applicants will be evaluated solely on the basis of their ability, competence, and performance of the essential functions of their positions.
