RTL Design Engineer The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals. • Develop HW architecture from specification documents. • Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL. • Develop and execute low power design (UPF/CPF). • Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc • Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties) • Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures. • Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break. • Take ownership of tasks and drive tasks to closure.
Requirements:- Bachelor's Degree in electrical or Computer Engineering or related field
- 7+ years of experience in Logic (RTL) Design
Qualifications:
5+ years of experience in one of the following 3 areas: CPU architectures (holistic view including instructions, translation, operating modes, and exception models), CPU toolchains (cross-compile with assembler, linker, linker descriptors, etc), CPU assembly coding (with the understanding of writing/debugging testcode)CPU, GPU - pipelines, control, Memories hierarchies, interconnects, caches, CPU, GPU (coherency, multilevel and distributed) Verification tool development - OO programming, CPU/GPU/fabric/SoC tool development. Strong scripting, C, C++, Python experience Extensive experience debugging designs as well as creating simulation environments In depth knowledge of verification principles, testbenches, stimulus generation, UVM/OVM, and coverage Scripting language such as Python or Perl preferred System Verilog functional coverage (coding, debugging, closure)
