DFT Engineer

Job Summary: We are looking for a skilled DFT/ATPG Engineer with 5+ years of hands-on experience in ASIC/SoC design and manufacturing test. The candidate should have strong knowledge of DFT fundamentals, ATPG, scan-based testing, MBIST, IO testing, and clock DFT. The role involves developing, analyzing, and debugging DFT/ATPG solutions and working closely with cross-functional semiconductor teams.

Roles & Responsibilities: Develop and implement DFT solutions for ASIC/SoC designs. Perform scan insertion, scan-chain verification, and DFT rule checks. Generate, analyze, and debug ATPG patterns. Improve fault coverage and analyze ATPG coverage reports. Work with stuck-at, transition, and other relevant fault models. Support MBIST implementation, memory testing, and diagnostics. Work on IO test methodologies and pin-level validation. Support clock DFT implementation and clock verification. Debug DFT, ATPG, scan-chain, and simulation issues. Collaborate with RTL, Design, Verification, Physical Design, and Test teams. Use industry-standard DFT/ATPG EDA tools. Support DFT verification, signoff, and post-silicon debug activities.

Experience: Level 5+ years of hands-on experience in DFT and ATPG for ASIC/SoC designs. Strong experience in scan, ATPG, MBIST, IO testing, and clock DFT.Experience with industry-standard DFT/ATPG EDA tools. Good scripting/debugging skills are preferred.

Education: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. Strong understanding of digital design and RTL fundamentals.