Senior CPU Physical Design Engineer (PPA & Signoff)

RosaicLabs Inc in Austin, TX seeks an experienced CPU Physical Design Engineer to drive macro-level and gate-level design decisions for high‑performance ASIC blocks. The role emphasizes timing, power, and area optimization across complex CPU datapaths and memory structures. You will collaborate with RTL, DFT, verification, and packaging teams to ensure successful PPA outcomes, and lead physical design flows and signoff procedures to meet aggressive silicon targets.