VIVA USA Inc. is seeking a Senior Silicon Design Engineer to drive RTL to GDS flows for high-speed datapath IP on site in Santa Clara, CA. You will lead automated synthesis, timing-driven place and route, CTS, clock gating, and power/area optimizations for advanced nodes.
Responsibilities include floor planning, design methodology, logic equivalence checks, and final IP signoff. Strong Verilog and multi-project coordination are essential for success.
