RTL Design Engineer, Google Cloud - Sunnyvale

Responsibilities: Create clock control subsystem micro-architecture specifications for ASICs Develop SystemVerilog RTL to implement clocking, reset, and timing-critical logic Collaborate with architecture, DV, and physical design teams to evaluate features and ensure timing closure Draft test plans with DV teams to verify RTL and debug designs Contribute to infra and methodology for chip management, error handling, and debug in SoCs Coordinate with software and system hardware counterparts in a cross-functional setting Support TPU architecture integration and data center accelerator RTL Participate in multi-stakeholder design and verification efforts

Key requirements: Bachelor in Electrical Engineering, Computer Engineering, or Computer Science; equivalent practical experience 2 years ASIC RTL design experience focusing on clocking, reset, or timing-critical RTL development SystemVerilog experience for microarchitecture specs and synthesizable RTL Python, Tcl, or Perl for automating design tasks and data analysis Experience with industry-standard EDA tools for simulation, synthesis, and power analysis Cross-functional collaboration Strong communication and coordination across software, hardware, and DV teams Self-driven and independent work style SystemVerilog ASIC RTL design Clocking/Reset/Timing optimization