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ASIC Design Engineer

mirafra technologiesSanta Clara, CALead L6
Mirafra Technologies in Santa Clara, CA is seeking a senior RTL engineer to translate system requirements into robust microarchitectures and drive HW/SW co-design across AI workloads and memory systems. You will collaborate with software teams to define programming models, interfaces, and data movement, while leading RTL implementations and architecture reviews to meet performance and power targets.
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Level

Lead L6

Location

Santa Clara, CA

Occupation

Computer Hardware Engineers

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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