Principal ASIC Physical Design Lead

Cisco Systems, Inc in Austin seeks a Senior Physical Design engineer to lead fullchip floorplanning and RTL-to-GDSII flows for 7nm/5nm processes. You will collaborate with RTL, DFT, implementation, EDA vendors, and tool teams to optimize performance, power integrity, and die size. The team focuses on silicon innovations like Silicon One, with opportunities to apply UPF low-power design methods and signoff strategies. Strong EE background essential and hands-on with major EDA tools required.