Principal / Senior Digital CPU Architect

We are seeking a visionary Digital CPU Architect to lead and drive the core computing architecture for our next-generation sensor processing SoCs. In this role, you will define and micro-architect low-power, high-efficiency processing cores, vector units, and domain-specific ISA extensions (e.g., RISC-V) optimized for edge AI and real-time signal conditioning. You will bridge software requirements with hardware execution, establishing performance, power, and area (PPA) trade-offs to power mission-critical edge-sensing applications. Key ResponsibilitiesCPU Core Architecture: Define and micro-architect embedded CPU and NPU cores, execution pipelines, branch predictors, cache hierarchies, and memory sub-systems tailored for ultra-low-power edge computing. ISA Definition & Custom Extensions: Evaluate open instruction set architectures and design custom vector, DSP, or edge AI acceleration extensions for sensor data processing. PPA Trade-off Analysis: Build performance models (Cycle-accurate / C++ / SystemC / Gem5) to analyze instruction throughout, memory bandwidth bottlenecks, latency, and power usage across target workloads. Cross-Functional Collaboration: Partner with digital RTL teams to guide implementation feasibility, physical design teams on timing/area budgets, and software/compiler teams to ensure seamless hardware-software co-design. Silicon Roadmap & Strategy: Drive technology roadmaps for next-generation compute engines, evaluating novel architectural techniques (e.g., domain-specific acceleration, decoupled execution) to keep products ahead of market demands. Qualifications & RequirementsEducation: Bachelor’s, Master’s, or Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related field, and 10+ years of experience. Core ExpertiseStrong working knowledge of open architectures and microarchitectures, including custom instruction set extension design. Hands-on proficiency in building architectural simulators and modeling frameworks (C++, SystemC, Gem5, or Python). Solid understanding of digital hardware implementation trade-offs (frequency, area, static/dynamic power, pipeline depth). Domain Knowledge: Experience with DSP architectures, SIMD/vector processing, cache coherency, and bus protocols (AMBA AXI/ACE/CHI). Silicon Success: Proven track record of taking complex CPU or hardware accelerator architectures from concept to functional silicon tape-out.