Senior ASIC Design & Verification Eng - Hybrid Sunnyvale

Salt in Sunnyvale, CA, is seeking an ASIC Design and/or Verification Engineer (Sr. to Principal) to design, verify and optimize high-performance networking chips in a hybrid work model. You will write Verilog/SystemVerilog, develop specs, mentor juniors, and collaborate with Physical Design to meet timing and power targets. Candidates have 4–15+ years of relevant experience and a strong background in architecture, verification, and scripting with Perl or Python.