Manager Digital Design (FPGA) Engineering - Rolling Meadows, IL

Epiq Solutions COMPANY BACKGROUND Epiq Solutions develops cutting-edge software-defined radio (SDR) products and processing solutions to enable spectrum dominance for maritime, land, air, and space domains. With 17 years serving government and commercial enterprise customers and 30K+ devices fielded to more than 500 customers, Epiq Solutions is a trusted partner with a proven heritage of delivering open architecture products in radically small form factors where time-to-market, cost, and performance are critical for mission success. For more information, visit https://epiqsolutions.com JOB OPENING Reporting to the Director of SDR Engineering, the Manager of FPGA Engineering leads a growing, geographically distributed FPGA engineering team supporting the Rolling Meadows, IL, engineering organization. This is a hands‑on engineering management role that combines direct contribution to FPGA development with responsibility for team leadership, development, and delivery. This role is a balance of individual technical contribution and management. The FPGA Manager will help define and execute the FPGA development strategy for Epiq's software‑defined radio products and processing solutions in partnership with engineering leadership. The individual will ensure FPGA development efforts align with product and organizational objectives while maintaining excellence in technical execution, quality, performance, schedule, and delivery. This leader will work closely with hardware, software, systems, test, project management, and other engineering disciplines throughout the product development lifecycle.

Provide technical leadership and oversight for FPGA architecture, RTL design, simulation, synthesis, implementation, timing closure, verification, integration, and troubleshooting across Epiq products and development programs. Contribute to FPGA-related engineering decisions across the organization. Personally contribute to selected FPGA architecture, design, verification, and troubleshooting efforts while delegating technical ownership and maintaining sufficient capacity to lead the team effectively. Collaborate with engineering and business stakeholders throughout the FPGA development lifecycle to align on technical roadmaps, project priorities, schedules, resource requirements, and deliverables. Lead the development and maintenance of credible FPGA effort, resource, and schedule estimates with the responsible engineers, clearly communicating assumptions, dependencies, uncertainty, and technical risks. Oversee and coordinate simultaneous FPGA development efforts, identify technical dependencies and emerging risks, and ensure adherence to schedule and scope. Guide the development and implementation of digital signal processing and high‑speed data processing functions within FPGA‑based SDR platforms. Evaluate and guide the selection and effective use of FPGA devices, development tools, IP, interfaces, and architectures, incorporating relevant advances in FPGA technologies and development practices. Ensure FPGA designs meet applicable performance, reliability, resource utilization, power, and other product requirements. Promote robust FPGA design and verification practices, including appropriate design reviews, simulation, test strategies, configuration management, and documentation. Represent Epiq Solutions in customer‑facing technical discussions as needed, contributing to solution definition and building confidence through strong technical expertise. Leadership Responsibilities Lead a growing team of FPGA engineers, managing assignments and capacity across new products, enhancements, and sustaining engineering within agreed priorities. Resolve resource conflicts within the team and bring cross‑program resource, scope, and schedule tradeoffs to engineering leadership with clear recommendations. Recruit, onboard, and retain FPGA engineering talent as the team and business continue to grow. Work with the team to improve FPGA development processes, tools, standards, and best practices to strengthen quality, predictability, efficiency, and team effectiveness. Promote reusable IP, shared verification assets, and knowledge transfer to reduce duplicated effort. Lead improvements to the FPGA aspects of product integration in collaboration with Hardware, Core Platform, Software, and Test teams, including integration, interface definition, and system‑level test and troubleshooting. Foster collaboration and build consensus within the team while utilizing sound judgment to make timely decisions and move efforts forward when necessary. Foster a team culture of technical ownership, accountability, collaboration, open communication, learning, and innovation. Support team members’ career development, technical growth, and professional advancement through regular 1:1 meetings, performance reviews, constructive feedback, coaching, and mentorship. Establish clear expectations and ensure team members understand priorities, responsibilities, and success measures. Address performance, accountability, and interpersonal concerns promptly and fairly, establishing clear improvement expectations and partnering with engineering leadership and HR as appropriate.

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related engineering discipline required; master's degree preferred. Minimum of 10 years of relevant FPGA/digital design engineering experience, including demonstrated delivery of FPGA‑based products or systems through integration, verification, and release. Strong FPGA architecture and RTL design experience using Verilog/SystemVerilog and/or VHDL; practical Verilog/SystemVerilog experience preferred. Demonstrated experience with FPGA simulation, synthesis, place‑and‑route, static timing analysis, timing closure, and design verification. Experience with modern FPGA development environments and toolchains; substantial AMD/Xilinx Vivado experience is strongly preferred. Experience developing and integrating FPGA IP and interfacing FPGA logic with processors, memory, converters, and high‑speed devices. Strong understanding of digital design fundamentals, clock‑domain crossing, reset architectures, synchronization, and high‑speed digital interfaces. Experience with source/version control and disciplined engineering configuration‑management practices. Demonstrated ability to troubleshoot complex FPGA and system‑level issues in a laboratory environment. Ability to provide meaningful technical direction and design oversight while enabling experienced engineers to maintain ownership of their work.