SoC Physical Integration Engineer - FPGA/ACAP

AMD in San Jose, CA is seeking an experienced SoC Physical Integration engineer to drive the tape-out readiness of FPGA/ACAP blocks. You will work with Architecture, CAD, Software, and Product Engineering across geographies to enable robust chip-level integration. Ideal candidates have FPGA expertise, Verilog, SPICE, and hands-on experience with 2nm/3nm nodes. This on-site role requires strong debugging and cross-functional collaboration across teams.