SK hynix memory solutions is seeking a Sr. Staff Physical Design Engineer to lead RTL-to-GDS implementation for advanced-node SoCs.
You will guide synthesis, placement, CTS, and routing while collaborating with front-end, DFT, power, and analog teams to optimize PPA and ensure silicon success. Requirements include 6+ years in ASIC physical design, strong expertise in STA and PrimeTime, and hands-on experience with Calibre for DRC/LVS/ERC.
