ASIC UVM Verification Engineer
Role:
Senior ASIC Verification Engineer Industry: Satellite Communications / Semiconductor Experience: 8+ years Key requirement: Strong hands-on SystemVerilog and UVM verification experience. What the client is looking for Multiple openings — candidates will be placed where their skills fit best. Three verification levels: IP/Block-level, Subsystem-level, and SoC-level. Well-rounded UVM engineers who can develop testbenches, debug complex designs, and drive verification to signoff. Space experience is a plus. DSP experience is a plus. Must-have technical skills SystemVerilog and UVM.ASIC/SoC functional verification. Verification planning, assertions, and functional coverage closure. Testbench development, scoreboards, reference models, and protocol monitors. RTL and testbench debugging. Complex digital control and datapath verification. Preferred experience Satellite, wireless, modem, or baseband communications. DSP pipelines, LDPC/BCH/FEC blocks, framing engines, or beamforming. Formal verification, CDC/RDC, low-power verification, and high-speed interfaces. Hardware/software integration and post-silicon debug.
Ideal candidate profile:
A senior UVM verification engineer with 8+ years of ASIC/SoC experience, strong SystemVerilog skills, and experience at one or more verification levels. Satellite or DSP expertise is beneficial but not mandatory.
