Astera Labs is hiring a Principal Design Verification Engineer to own the functional verification of our high-speed SerDes/PHY IP—the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success at the analog/digital boundary.
You will partner with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks used in PCIe Gen 6/Gen 7,
