Amiseq Inc. in Palo Alto seeks an experienced IC Physical Design Engineer to own end-to-end physical design flows, including floorplanning, placement, CTS, routing, and signoff across modern nodes.
The role emphasizes timing closure, power integrity, and multi-voltage strategies in a fast-paced semiconductor environment. The candidate will collaborate with RTL and micro-architecture teams, as well as Foundry and CAD groups, to debug complex timing, congestion, and power issues and drive design
