NUVACORE in Santa Clara is seeking a Custom Memory Design Engineer to drive end-to-end memory development—from schematic design to tape-out—while optimizing PPA across advanced CMOS nodes. You will own memory IP signoff and collaborate with foundry, CAD, RTL, and DFT teams to ensure robust performance.
The role demands hands-on transistor-level design, SPICE accuracy, and a track record of silicon-validated memory IP in high-volume products, with strong communication across teams.
