Job Title: Principal III-V Photonic Chip Design / Fabrication Engineer
Location: Fremont, CA
Compensation: $200K - $300K Depending on Experience
Requirement: III-V Photonic Integrated Circuits (PIC), DFB Lasers, High-Speed Modulators (EML, EAM, MZM), III-V Epitaxy & MQW Design, Foundry Process Development
Position Overview:
We are seeking someone with expertise in III-V photonic chip development. This candidate will be responsible for developing advanced photonic chips to support next-generation communications in data center networks and AI clusters.
Responsibilities will include:
III-V EPI and device designs for fabricating at an external foundry, working with foundry to optimize the fabrication process, and test data analysis. This candidate is expected to innovate in III-V high-speed design and fabrication and bring it from design to production. This position is at principal level or above. This candidate must have a deep understanding of III-V photonic material, devices, and the associated fabrication process, and must be able to optimize the fabrication process to improve the device performance and yield. In addition, the candidate must have successful experience of leading at least one of the following developments:1) High power (>=100mW) DFB lasers in O-band or C-band.2) High-speed (>=100Gb/s) EML.3) High-speed (>=100Gb/s) III-V EAM or MZM.
Key Responsibilities:
Design III-V EPIs, including multiple quantum-well (MQW) layers and waveguiding layers, for various III-V devices.
Design III-V devices, including high-speed modulators, high-speed photodetectors, and DFB lasers.
Design various photonic integrated circuits (PICs) incorporating III-V devices for high-speed optical communications.
Perform various simulations, such as optical mode simulation, high-speed RF simulation, quantum well absorption and index modulation simulation, and laser cavity simulation.
Work with external foundries for III-V chip manufacturing and for fabrication process improvement.
Plan for electrical, high-speed RF, and optical testing, and analyze test data.
Interact with packaging and module teams for chip performance evaluations in the modules.
Qualifications:
Master's or higher degree in Electrical Engineering, Semiconductor Physics, Optical Communications, or other related fields.
Direct experience in III-V material, quantum well designs, device designs, device fabrication, and device testing is highly preferred.
Skilled in optical simulation, high-speed RF modeling, laser cavity modeling, and characterization, and familiar with related software.
Some knowledge of Si photonic devices and circuits, pluggable and co-packaged optical transceivers, is desirable.
Some experience in III-V device failure and material defects analysis is desirable.
Excellent analytical and problem-solving abilities.
Strong communication skills and a proven ability to work both independently and as part of a team.
Benefits: Medical/Dental/Vision Vacation/PTOBonus 401K
