Allegro MicroSystems is seeking a Principal Mixed-Signal Design Verification (MSDV) Engineer & Team Lead to drive the verification of next-gen Power ICs, including motor drivers and PMICs. You will lead a verification team from planning to tape-out sign-off.
The role requires 8+ years in MSDV, expertise in SystemVerilog/UVM/SVA, and strong background in power topologies. You will collaborate with design and systems teams, build scalable testbenches, and advance automation in a global
