Senior SoC Physical Design Lead

NXP Semiconductors in Austin, TX, seeks an experienced Principal Physical Design Engineer to own end-to-end SoC PD from RTL to GDSII for advanced nodes. You will lead floorplanning, placement, routing, signoff and post-silicon support, targeting tight PPA and tapeout readiness. You will mentor teams, drive PD methodologies, collaborate with architecture, RTL, verification, and EDA vendors, and push automation for 5nm and beyond.