PCIe Timing Analysis Engineer Perform static timing analysis (STA) for the PCIe subsystem within the Sparta architecture. Develop, validate, and maintain PCIe-specific timing constraints (SDC) and exceptions. Run full chip and block level STA for PCIe paths across PVT corners and operating modes. Identify timing violations and drive ECO recommendations to close setup/hold, DRV, and noise issues. Collaborate with RTL, synthesis, PnR, and verification teams to ensure end to end PCIe timing signoff. Analyze clocking, resets, CDC paths, and PHY interface timing for PCIe. Generate timing reports and signoff documentation for program milestones. Support timing debug during subsystem integration and final tape out.
Qualifications:- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or related field.5+ years of experience in static timing analysis for complex SoC designs
- Expertise with STA tools (PrimeTime or equivalent).Strong understanding of PCIe architecture, PHY interfaces, and timing requirements.
- Hands on experience developing and debugging SDC constraints and timing exceptions.
- Solid knowledge of clocks, resets, CDC, and hierarchical timing closure.
- Familiarity with synthesis, PnR flows, and ECO methodologies.
- Ability to interpret timing reports and drive closure across setup, hold, and DRV issues.
- Strong cross functional communication skills to work with RTL, physical design, and DFT teams.
