Senior STA Engineer: Tape-out Timing & Signoff Expert

Chiparama Inc. is seeking an experienced STA engineer to lead timing and signoff for high-performance SoCs. You will own block-level and full-chip SDC constraints, run STA/signoff with PrimeTime or Tempus, and collaborate with Physical Design, RTL and methodology teams through tape-out. You will debug timing violations, develop ECOs, and perform signoff analyses (OCV/AOCV/POCV) while building STA flows in Tcl, Python and Perl.