Senior STA & Timing Signoff Engineer (FinFET)

Central Business Solutions, Inc. is seeking Static Timing Analysis engineers to strengthen the timing signoff team for an advanced SoC project. You will own timing constraints, drive block- and full-chip timing closure across modes and corners, and collaborate with the PD, synthesis, and DFT teams to deliver silicon-ready timing signoff. The ideal candidate has strong fundamentals in STA, hands-on PrimeTime/PrimeTime SI and MMMC experience, with exposure to advanced FinFET nodes.