Senior ASIC RTL Engineer - DFT & SoC Design

Cisco Systems, Inc. in San Jose, CA, is seeking a senior RTL design engineer focused on Design for Test (DFT) for Silicon One. You will collaborate with front-end RTL and backend physical design teams to deliver robust silicon solutions and ensure performance and reliability. The role requires 7+ years in Electrical/CS engineering, strong Verilog/System Verilog, and experience with front-end tools (simulators, linting, CDC, synthesis, formal verification).