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Cisco Systems, Inc. is seeking a senior engineer for the Silicon One development organization to push high-quality DFT RTL and robust silicon solutions, collaborating with front-end RTL and backend physical design teams to align with Cisco's scalable architecture. The role requires a EE degree and Verilog/SystemVerilog expertise, front-end tools, and experience with AMBA, JTAG, and memories, with a US/Canada salary range disclosed in the posting.

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Level

Lead L6

Location

San Jose, CA

Occupation

Computer Systems Engineers/Architects

Industry

Semiconductor and Related Device Manufacturing

Posted

yesterday

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