Tech Lead, Verification Engineering - Connectivity
astera labsSan Jose, CA
Tech Lead, Verification Engineering - Connectivity
astera labsSan Jose, CALead L6
Computer Systems Design ServicesSemiconductor and Related Device ManufacturingElectronic Connector Manufacturing
APPLY NOW (opens in a new tab)Astera Labs in San Jose, CA is seeking an experienced Tech Lead Engineer, Design Verification to define and deliver robust verification for next-generation connectivity silicon enabling rack-scale AI infrastructure.
You will partner with RTL, architecture, firmware, and post-silicon teams to build verification strategies for high- bandwidth protocols and drive coverage closure from planning through silicon readiness.
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Level
Lead L6
Location
San Jose, CA
Occupation
Computer Hardware Engineers
Industry
Computer Systems Design Services
Posted
yesterday