Lead Processor Verification Architect

Cadence is seeking a Design Verification Team Director in California or Austin to lead the Processor Verification team. You will verify microprocessor cores and peripherals, craft verification plans, and implement testbenches with coverage closure. You will coordinate with DV/Arch/Design/FW teams and report on a 7-10 engineer group. The role demands 17+ years in design verification, a BS in EE/CE, strong leadership, and deep knowledge of SystemVerilog/UVM, plus scripting skills (Perl/Unix